Chapter 3
This chapter describes a typical design cycle in the implementation of a signal processing application. The first step in the cycle is to capture the requirements and specifications (R&S) of the system. The R&S usually specify the sampling rate, a quantitative measure of the system’s performance, and other applicationspecific parameters. The R&S constrain the designer to explore different design options and algorithms to meet them in the most economical manner. The algorithm exploration is usually facilitated by MATLAB®, which is rich in toolsets, libraries and functions. After implementation and analysis of the algorithm in MATLAB®, usually the code is translated into higher level programming languages, for example, C/++or C#.
This requires the chapter to focus on numbering systems. Representing signed numbers in two’s complement format is explained. In this representation, the most significant bit (MSB) has negative weight and the remainder of the bits carry positive weights. Although the two’s complement arithmetic greatly helps addition and subtraction, as subtraction can be achieved by addition, the negative weight of the sign bit influences multiplication and shifting operations. As the MSB of a signed number carries negative weight, the multiplication operation requires different handling for different types of operand. There are four possible combinations for multiplication of two numbers: unsigned–unsigned, signed–unsigned, unsigned–signed and signed–signed. The chapter describes two’s complement multiplication to highlight these differences. Scaling of signed number is described as it is often needed while implementing algorithms in fixedpoint format.
Characteristics of two’s complement arithmetic from the hardware (HW) perspective are listed with special emphasis on corner cases. The designer needs to add additional logic to check the corner cases and deal with them if they occur. The chapter then explains floatingpoint format and builds the rationale of using an alternate fixedpoint format for DSP system implementation. The chapter also justifies this preference in spite of apparent complexities and precision penalties. Cost, performance and power dissipation are the main reasons for preferring fixedpoint processors and HW for signal processing systems. The fixedpoint implementations are widely used for signal processing systems whereas floatingpoint processors are mainly used in feedback control systems where precision is of paramount importance. The chapter also highlights that currently integrated high gate counts on FPGAs encourages designers to use floatingpoint blocks as well for complex DSP designs in hardware.
The chapter then describes the equivalent format used in implementing floatingpoint algorithms in fixed point form. This equivalent format is termed the Qn.m format. All the floatingpoint variables and constants in the algorithm are converted to Qn.m format. In this format, the designer fixes the place of an implied decimal point in an Nbit number such that there are n bits to the left and mbits to the right. All the computations in the algorithm are then performed on fixedpoint numbers.
The chapter gives a systematic approach to converting a floatingpoint algorithm in MATLAB® to its equivalent fixedpoint format. The approach involves the steps of levelization, scalarization, and then computation of ranges for specifying the Qn.m format for different variables in the algorithm. The fixedpoint MATLAB code then can easily be implemented. The chapter gives all the rules to be followed while performing Qn.m format arithmetic. It is emphasized that it is the developer’s responsibility to track and manage the decimal point while performing different arithmetic operations. For example, while adding two different Qformat numbers, the alignment of the decimal point is the responsibility of the developer. Similarly, while multiplying two Qformat signed numbers the developer needs to throw away the redundant sign bit. This discussion leads to some critical issues such as overflow, rounding and scaling in implementing fixedpoint arithmetic. Bit growth is another consequence of fixedpoint arithmetic, which occurs if two different Qformat numbers are added or two Qformat numbers are multiplied. To bring the result back to predefined precision, it is rounded and truncated or simply truncated. Scaling or normalization before truncation helps to reduce the quantization noise. The chapter presents a comprehensive account of all these issues with examples.
For communication systems, the noise performance of an algorithm is critical, and the finite precision of numbers also contributes to noise. The performance of fixedpoint implementation needs to be tested for different ratios of signal to quantization noise (SQNR). To facilitate partitioning of the algorithm in HWand SWand its subsequent mapping on different components, the chapter describes algorithm design and coding guidelines for behavioral implementation of the system. The code should be structured such that the algorithm developers, SW designers and HW engineers can correlate different implementations and can seamlessly integrate, test and verify the design and can also fall back to the original algorithm implementation if there is any disagreement in results and performance. FPG Avendors like Xilinx and Altera in collaboration with Mathworks are also providing Verilog code generation support in several Simulink blocks. DSPbuilder from Altera and System Generator from Xilinx are excellent utilities. In a Simulink environment these blocksets are used for model building and simulation. These blocks can then be translated for HW synthesis. Amodel incorporating these blocks also enables SW/HWcosimulation. This cosimulation environment guarantees bit and cycle exactness between simulation and HW implementation. MATLAB® also provides connectivity with ModelSim though a Link to ModelSim utility.
Logic and arithmetic shifts of numbers are discussed. It is explained that a full analysis should be performed while converting a recursive digital system to fixedpoint format. Different computational structures exist for implementing a recursive system. The designer should select a structure that is least susceptible to quantization noise. The MATLAB® filter design toolbox is handy to do the requisite analysis and design space exploration. The chapter explains this issue with the help of an example. The chapter ends by giving examples of floatingpointCcode and its equivalent fixedpoint C conversion to clarify the differences between the two implementations. To explain different topics in the chapter several numerical examples are given. These examples use numbers in binary, decimal and hexadecimal formats. To remove any confusion among these representations, we use different ways of distinguishing the formats. Abinary number is written with a base 2 or b, such as 1001b and 1002. The binary numbers are also represented inVerilog format, for example 30b1001. Decimal numbers are written without any base or with a base 10, like 0.678 and 0.67810. The hexadecimal representation is 0x23df.
